High performance integrated circuits are driving the demand for high performance sockets, such as those disclosed herein and in U.S. Pat. Nos. 6,247,938; 6,409,521; 6,939,143; 6,957,963; 6,830,460; 7,114,960; 7,121,839; and 7,160,119, which are hereby incorporated by reference. As bus architectures becomes increasingly complex the frequency of the signals is much higher and more sensitive to changes in impedance. Next generation systems are running at about 5 GHz. High performance sockets, such as those identified above, have decreased pin pitch from about 1 millimeter (“mm”) to about 0.4 mm to about 0.5 mm and pin count is increasing.
This decrease in pitch creates at least two major problems. First, it is difficult and expense to manufacture printed circuit boards with pitches on the order of about 0.4 mm to about 0.5 mm that correspond to the pitch of high performance socket assemblies. Second, there are times during the validation and testing of integrated circuits where the user of such socket assemblies may desire to isolate individual signals or a group of signals independently from the routing of the associated printed circuit board (“PCB”).
Regarding the validation and testing problem, users currently design the printed circuit board in such a way to permit a spring probe to access the desired circuit trace that leads to the signal of interest. This probe access point is of a known distance from the signal source, and the user can interconnect a Logic Analyzer to understand the response of the silicon under known conditions. Test socket contact-resistance (Cres) and impedance mismatch is becoming of greater concern and spring probes have reached their electrical limits.
In many cases, there is no convenient location to place the probe access point on the top surface of the PCB, so designers locate points on the underside of the PCB near the device. This area of the PCB, however, is often loaded with other components such as decoupling capacitors, and in many cases a support plate to prevent PCB flexure when using a socket that covers many possible probe locations. This problem is compounded by the increase in multi-chip packages.